When Electronics magazine published a short article by a Fairchild Semiconductor engineer named Gordon Moore on April 19, 1965, few could have imagined that a single observation would become the organising principle of an entire industry. Moore noticed that the number of components on an integrated circuit had been roughly doubling every year, and he predicted the trend would continue for at least a decade. In 1975, he revised the pace to every two years. The rest is history — but the history is far more complicated, and more interesting, than the tidy slogan suggests.
The Numbers Behind the Prediction
In 1971, Intel’s 4004 processor — the first commercially available single-chip microprocessor — contained 2,300 transistors fabricated on a 10-micrometre process. By 2023, Apple’s M2 Ultra packed 134 billion transistors. That is roughly a five-million-fold increase in about five decades. No other industrial metric in human history has compounded like that for so long.
But Moore’s Law was never really a law of physics. It was an economic prediction, and for decades it held because of a virtuous cycle: shrinking transistors made them faster, cheaper, and more power-efficient simultaneously. This was formalised by Robert Dennard and colleagues at IBM in 1974, whose “scaling theory” showed that if you shrank transistor dimensions by 30%, you could pack in twice as many, run them faster, and keep power density constant. For roughly three decades, Dennard scaling delivered free performance.
The Day the Music Stopped
Around 2005-2006, Dennard scaling broke down. Leakage currents — the tendency of electrons to tunnel through ever-thinner insulators — meant that power density began rising again as transistors shrank. Clock speeds, which had climbed from a few megahertz in the early 1980s to over 3 GHz by the mid-2000s, essentially flatlined. The industry pivoted to multicore designs and specialised accelerators rather than raw frequency gains.
Then Moore’s Law itself came under pressure. The cost of building a leading-edge fab has ballooned: a modern 3-nanometre facility costs in the range of $15-20 billion, and TSMC’s total 2024 capital expenditure ran to roughly $30 billion. ASML, the Dutch company that holds a de facto monopoly on the extreme ultraviolet (EUV) lithography systems required for the most advanced nodes, sells each machine for well over $150 million; its next-generation High-NA EUV tools cost around €350 million apiece.
Why the Law Keeps Breathing
Yet the industry has repeatedly found escape routes. The transistor itself was reinvented in 2011 when Intel introduced FinFETs, raising the channel into a three-dimensional fin to improve electrostatic control. At the 3nm node, Samsung and TSMC moved to gate-all-around (GAA) architectures — nanosheet transistors where the gate wraps the channel on all four sides. TSMC’s N3 and Intel’s 18A process both represent this next generation.
Packaging has become as important as the transistors themselves. Rather than cramming everything onto one giant die, companies now use chiplets — smaller dies assembled into a single package — and advanced 3D stacking. AMD’s chiplet-based Ryzen and EPYC processors are the clearest commercial proof, and TSMC’s CoWoS (Chip-on-Wafer-on-Substrate) packaging is the bottleneck for AI accelerator supply.
The Economics Have Inverted
Here is the twist that makes Moore’s Law’s 60th birthday bittersweet: transistors are no longer getting cheaper per unit at the historic rate. Leading-edge wafer prices have risen faster than density. A 5nm wafer from TSMC reportedly costs around $16,000-17,000, and 3nm wafers closer to $18,000-20,000. Meanwhile, the older 28nm node remains a workhorse precisely because it is cheap.
This means the cutting edge is increasingly reserved for applications that can justify the cost: high-performance computing, AI accelerators, flagship smartphones, and advanced networking. For most chips — microcontrollers, power management, automotive sensors — the economics favour maturity over miniaturisation. The industry has bifurcated into a bleeding-edge frontier and a vast, profitable trailing edge.
What Comes Next
Several paths are being explored. Backside power delivery, in which the power network is moved to the underside of the wafer, reduces resistance and frees up routing space on top. Intel’s 18A and TSMC’s N2 both incorporate variants of this idea. New materials such as molybdenum disulfide and carbon nanotubes are under investigation for channels below 1nm. And a 2D-material transistor could, in principle, extend scaling for another decade.
Beyond silicon, there is the emerging field of spintronics and photonics, plus the growing use of specialised architectures — TPUs, NPUs, and neuromorphic chips — that abandon the general-purpose model entirely.
The Canadian Angle
For Canada, the semiconductor story is one of strategic vulnerability and selective strength. The country has no leading-edge fab, but it is home to a dense cluster of chip design firms, photonics companies, and the Montreal-based AI hardware research ecosystem. The federal government’s 2024 commitment of hundreds of millions of dollars to semiconductor packaging and photonics reflects an awareness that owning the frontier is less realistic than owning niches.
The Investment Race Behind the Nanometre
No discussion of Moore’s Law is complete without the capital that sustains it. Semiconductors are now a matter of national strategy. The United States passed the CHIPS and Science Act in 2022, committing $52.7 billion in subsidies for domestic manufacturing and research. The European Union followed with its own Chips Act, targeting 20% of global production. Japan, South Korea, and Taiwan have all expanded incentive programmes. The logic is simple: whoever controls advanced logic and memory controls the foundation on which AI, defence, and communications systems are built.
The results are visible in construction. TSMC is building fabs in Arizona, Japan, and Germany. Intel has committed to new capacity in Ohio and Arizona. Samsung is expanding in Texas. These projects take years to come online and cost tens of billions each, but they represent a geopolitical hedge against the concentration of advanced production in a single, geopolitically exposed island.
The Talent Constraint
Fabs are only as good as the people who run them. Advanced semiconductor manufacturing requires process engineers, lithography specialists, and materials scientists — a workforce that takes years to train and is concentrated in a handful of regions. Every new fab competes for the same limited pool. Universities in the U.S., Taiwan, South Korea, and Europe have expanded semiconductor curricula, but the gap between demand and supply remains wide. Immigration policy, once an afterthought in industrial strategy, has become central to it.
What “Nanometre” Really Means
A word on terminology, because it confuses even informed readers. The “3nm” or “5nm” label attached to a process node no longer corresponds to any physical dimension of the transistor. It is a marketing name for a generation of manufacturing technology. The actual gate lengths and pitches are larger, and different foundries’ nodes are not directly comparable. TSMC’s “N3” and Samsung’s “3nm” are built differently and perform differently. What matters in practice is density (transistors per square millimetre), performance, and power efficiency — not the number on the label.
The Memory and Storage Dimension
Moore’s Law discussions often focus on logic, but memory has followed its own curves. DRAM scaling slowed earlier than logic, and the industry responded by stacking layers vertically — 3D NAND flash, now exceeding 200 layers, is the clearest example. High Bandwidth Memory (HBM), which stacks DRAM dies and connects them with through-silicon vias, has become a critical component for AI accelerators. HBM3E and its successors are manufactured in limited quantities and are one of the tightest bottlenecks in the AI supply chain, commanding premium prices.
Analog, Power, and the Physical World
For all the focus on digital scaling, much of the chip industry serves the analog and power domains — sensors, radio frequency components, power management ICs. These are built on mature nodes (often 28nm, 40nm, or larger) because analog circuits do not benefit from miniaturisation the way digital logic does. The industry’s trailing edge is not obsolete; it is where the physical world meets silicon. Automotive, industrial, and medical applications depend on it, and shortages in mature nodes during the pandemic demonstrated how indispensable these “boring” chips are.
Heat: The Invisible Ceiling
Every transistor that switches produces heat. As density rises, removing that heat becomes a first-order engineering problem. Air cooling is reaching its limits for high-performance chips, and the industry is moving to liquid cooling — direct-to-chip cold plates, immersion cooling, and in some designs, microfluidic channels etched into the silicon itself. Data centres running AI accelerators are already adopting liquid cooling at scale. The heat problem is not a footnote; it is one of the reasons chip design has shifted toward efficiency and specialisation rather than raw clock speed.
The Quantum Wildcard
Beyond classical scaling, quantum computing promises a fundamentally different model of computation. IBM, Google, and a host of startups are building qubit-based machines, and the error-correction milestones achieved in recent years have been genuine. But quantum computers will not replace classical ones for most tasks; they will address specific problems — factoring, certain optimisation and simulation tasks — where classical machines are inefficient. For the foreseeable future, classical scaling and quantum development will proceed on separate tracks.
Conclusion
Moore’s Law was never a guarantee. It was a prediction about a business model, and when that model’s physics hit a wall, the industry rebuilt the model around it. Sixty years on, the pace of improvement has slowed in the traditional sense, but the range of levers — architecture, packaging, materials, and specialised silicon — has multiplied. The transistor count may no longer double like clockwork, but the silicon age is far from over. If anything, the scramble for AI compute has made semiconductor strategy a matter of national policy, which suggests the next chapter will be written in capitals as much as in cleanrooms.
